1. Field of the Invention (Technical Field)
The present invention relates to gallium nitride (GaN) junction field-effect transistors (JFETs) and to methods of making such transistors.
2. Background Art
Gallium nitride (hereinafter GaN) is an attractive material for use in high temperature, high power electronic devices due to its high bandgap (3.39 eV), high breakdown field (.about.5.times.10.sup.6 V/cm), high saturation drift velocity (2.7.times.10.sup.7 cm-s.sup.-1), and chemical inertness. Morkoc, et al., J. Appl. Phys. 76(3), p. 1363, Aug. 1, 1994. Metal semiconductor FETs (MESFETs), high electron mobility transistors (HEMTs), heterostructure FETs (HFETs), and metal insulator semiconductor FETs (MISFETs) have all been developed using epitaxial AIN/GaN structures. Khan, et al, Appl. Phys. Lett. vol. 62, p. 1786 (1993); Khan, et al., Appl. Phys. Lett. vol. 63, p. 1214 (1993); Binari, et al., Proc. 1994 ISCS, 9/94, Inst. Phys., Bristol, UK, pp. 492-496 (1995); and PCI Proceedings, pp. 353-365, October 1986.
The patent literature also describes the use of GaN. U.S. Pat. No. 4,985,742, to Pankove, entitled "High Temperature Semiconductor Devices Having at Least One Gallium Nitride Layer", discloses the application of GaN layers to other semiconductors to act as a contact or window layers. No JFET use or structure is disclosed. U.S. Pat. Nos. 5,192,987 and 5,296,395, to Khan, et al., respectively titled "High Electron Mobility Transistor with GaN/Al.sub.x GA.sub.1-x N Heterojunctions" and "Method of Making a High Electron Mobility Transistor", both disclose the use of GaN which is epitaxially doped, lacks a p/n junction gate, and lacks p-type doping.
The use of ion implantation doping in semiconductor devices employing GaAs JFET's was described by Zolper, et al., "An All-Implanted, Self-Aligned, GaAs JFET with a Nonalloyed W/p.sup.+ -GaAs Ohmic Gate Contact", IEEE Transaction on Electron Devices, vol. 41, pp. 1078-1082, July, 1994; Sherwin, et al., "An All Implanted Self-Aligned Enhancement Mode n-JFET with Zn Gates for GaAs Digital Application," IEEE Electron Device Letters, vol. 15, pp. 242-244, July, 1994; and Zolper, et al., "Enhanced High-Frequency Performance in a GaAs Self-Aligned, n-JFET Using a Carbon Buried p-Implant," IEEE Electron Device Letters, vol. 15, pp. 493-495, December 1994.
GaN thin films have been developed in the prior art by epitaxial growth on c-sapphire. Yuan, et al., "High Quality P-Type GaN Deposition on c-Sapphire Substrates in a Multiwafer Rotating-Disk Reactor", J. Electrochem Soc., vol. 142, pp. L163-L65, September 1995. Such GaN films have also been ion implanted, that is, n- and p-type regions have been produced in GaN using Si.sup.+ and Mg.sup.+ /P.sup.+ implantation and subsequent annealing. Pearton, et al., entitled "Ion Implantation Doping and Isolation of GaN," Appl. Phys. Lett. vol. 67, pp. 1435-1437, September 1995. Electron cyclotron resonance (ECR) etching of GaN films in various gaseous plasmas has also been accomplished in the prior art. Shul, et al., "Plasma Chemistry Dependent ECR Etching of GaN," Mater. Res. Soc., Symposium AM, November 1995.
The prior art fails to disclose, however, production of a GaN JFET fabricated with ion implantation doping, as noted by recent publications of Applicants. Zolper, et al., "Ion-Implanted GaN Junction Field Effect Transistor," Appl. Phys. Lett., vol. 68, pp. 2273-2275 , 15 Apr., 1996; Zolper, et al., "III-Nitride Ion Implantation and Device Processing", Electrochemical Society Meeting, May 1996; Zolper, et aL, "Gallium Nitride Junction Field Effect Transistor for High Temperature Operation", 3rd International High Temperature Electronic Conf., June 1996; and Zolper, et al., "P- and N-Type Implantation Doping of GaN with Ca and O", Materials Research Society April 1996.